The present disclosure relates to voltage translation circuits, and, in particular, to an apparatus for providing voltage translation for a mixed voltage circuit.
Integrated circuits (ICs) are being developed which contain core logic that operates at comparatively low voltages. At the same time, this core logic must interface with output buffer circuits that generally operate at higher voltages to provide greater output current and higher output voltages. To accommodate such a voltage difference, voltage translator circuits are often used in order to translate the low voltage output from the core logic to the higher voltage required for operation of the higher voltage circuits, for example, output buffer circuits.
Recent developments in IC design and fabrication have resulted in the core logic of ICs having even lower voltage requirements. As the voltage level required to drive the core logic decreases to below 1 Volt (V), however, traditional voltage translator circuits are inadequate and result in an erroneous output to the higher voltage circuit. Such inadequacy results because traditional voltage translator circuits operate only as long as the lower voltage (driving the IC core logic) exceeds a minimum threshold voltage, VTH, (e.g., 0.7 V to 0.9 V) required to operate xe2x80x9chigh voltagexe2x80x9d transistors commonly used in the voltage translators, generally by at least 300-400 millivolts (mV). The output voltages from modern ICs having the lower voltage IC core logic, however, may not sufficiently exceed the minimum threshold voltage (VTH) to sufficiently turn on the higher voltage transistors and thereby compromise voltage translator operation.
For example, core logic is being developed to operate at only 0.9 V. When coupled to a gate of a higher voltage transistor used in standard translation circuits, the 0.9 V output voltage from the core logic is insufficient to turn on such a higher voltage transistor, resulting in anomalous operation.